A variety of three-dimensional structures for stacked capacitors fabricated within a monolithic integrated circuit have been proposed. The fabrication of these structures generally adds a great deal of complexity to the manufacturing process. In addition, incomplete structures may be very delicate, requiring inordinate care during wafer handling to avoid structure breakage that could result not only in defective cells, but also in particle contamination elsewhere in the array. The DRAM cell structure proposed by T. Ema of Fujitsu Corporation at the 1988 International Electron Devices Meeting in San Francisco, California (592-595 IEDM 88) is an example of such a structure. The polysilicon fins, from which the cell capacitor plates are constructed must remain exposed and unsupported during many process steps. In addition, exceptional conformality of deposited nitride and polysilicon layers is essential to the fabrication process. If inter-fin gaps are not maintained within a narrow range of 500-1000.ANG., conformal deposition of the cell dielectric and cell plate layers becomes nearly impossible.
The stacked capacitor structure that is the subject of U.S. Pat. No. 4,827,323 issued to Howard L. Tigelaar, et al, of Texas Instruments Inc. on May 2, 1989, has several advantages over the Fujitsu device described above, in that the capacitor structure never experiences a delicate stage wherein it is vulnerable to breakage. In addition, deposition and clearance parameters are not as stringent. The stacked capacitor disclosed by Tigelaar, et al, consists of first and second series of interleaved plates, each plate of the first series being insulated from an adjacent plate of the second series by a thin dielectric layer. Each plate of the first series is interconnected along an edge thereof with other plates of the first series by a first interconnection layer. Dielectric borders insulate the edges of plates pertaining to the second series from the first interconnection layer. Likewise, each plate of the second series is interconnected by an edge thereof with other plates of the second series by a second interconnection layer. Dielectric borders insulate the edges of plates pertaining to the first series from the second interconnection layer. In order to facilitate the creation of the dielectric borders, the first series plates are made from a first material (e.g., molybdenum), which can be selectively etched with respect to both a second material (e.g., doped polysilicon), from which the second series of plates are fabricated, and a third material (e.g., silicon dioxide) from which the thin dielectric layers are fabricated. The dielectric borders, themselves, require the deposition of yet an additional layer. This multiplicity of materials and large number of deposition steps complicates the fabrication process to the point where other capacitor designs may more attractive.
What is needed is an improved capacitor having a configuration similar to that of Tigelaar, et al, the fabrication of which requires the deposition of only two materials, one for both series of conductive layers and dielectric borders, and the other for the dielectric layers.